A flash EEPROM is a memory device that typically includes a memory array having field-effect memory cells. Each memory cell typically includes a source region, a drain region, a channel region, a tunnel dielectric layer, a floating gate layer, a control gate layer, and an intergate insulating layer (between the control gate layer and the floating gate layer). In the flash EEPROM, the floating gate layer typically has a charge state, which is a programmed state or an erased state. When the floating gate layer is in a programmed state, the floating gate layer has a relatively high number of electrons. The electrons typically lower the floating gate potential below the threshold voltage of the cell. When a programmed cell is at read biasing conditions, the cell typically has a relatively low current flow through its channel. When the floating gate layer is in an erased state, the floating gate layer has a relatively low number of electrons. Fewer electrons cause a higher floating gate potential that is typically above the threshold voltage of the cell. When an erased cell is at read biasing conditions, the cell has a relatively high current flow through its channel.
For one prior art flash EEPROM, the charge state of the floating gate layer may be changed by programming the cell using hot electron injection through the drain side or by erasing the cell using Fowler-Nordheim tunneling through the source side. A prior art flash EEPROM has been found to have a limited number of cycles. After about 10,000 cycles, the cell's programming and erasing efficient is typically lowered. The lower efficiency is believed to be due to electrons and holes trapped in the tunnel dielectric layer. The trapped charge can reduce the effective field across the layer and slow down the programming or erasing process. After about 100,000 cycles, the cell typically can no longer be programmed or erased properly.
Programming performance of the cell is typically improved by increasing the channel dopant concentration near its drain region. The higher channel doping concentration causes a relatively high channel current and electric field near the drain region and allows sufficient generation of hot electrons near the drain region. However, the increased dopant concentration typically lowers the source-substrate breakdown voltage because the breakdown voltage generally decreases as the channel doping concentration increases. The source potential during erase is typically limited by the source-substrate diffusion junction breakdown voltage. If the device is erased when the source potential is higher than the source-substrate diffusion junction breakdown voltage, reliability problems including damage to the tunnel oxide-substrate interface and hole accumulation within the tunnel oxide layer may occur. As the device is cycled more times, the device is more likely to become non-functional because of the reliability problems. If the channel doping concentration is lowered to give a higher source-substrate diffusion junction breakdown voltage, the programming performance is typically not optimized. Therefore, one typically chooses to optimize the programming performance of the cell or the erasing performance of the cell.